# The kernel you boot

The source holds every architecture. Context is the one this build keeps.

[Book a demo](https://byteask.cal.com/pratyush/book-a-demo) [See the evidence](https://byteask.ai/industries/systems#evidence)

## The build gives the context

ByteAsk Context indexes the functions and calls your compile commands select. The examples below show what was captured for this domain.

The problem

Arch #ifdefs, inlines, and macros. Text search shows every one

This recording

No arch header is resolved. Layout is read from the binary with pahole

The speed number below is the benchmark, not a resolved #ifdef.

[How ByteAsk Context works](https://byteask.ai/context)

## Read the layout. Measure the fix.

A four-shard benchmark. Adjacent SymbolStats records shared a cache line. alignas(64) separates those records. 2.39x over 9 runs, above the noise gate.

This is a C++ market-data benchmark, not a kernel recording.

Layout from the binary. The speed claim has to clear the noise gate.

```
SymbolStats: size 32  (source: pahole (exact))
Method: plain timing (perf unavailable) (repeat=9, warmup=1 untimed)
A: mean 0.1903s over 9 run(s) (±0.0016s stderr)
B: mean 0.0795s over 9 run(s) (±0.0004s stderr)
B is 2.39x faster than A (delta 0.1108s > noise gate 0.0041s; significant).
-struct SymbolStats {
+struct alignas(64) SymbolStats {
```

Recorded 2026-09-11.

Read the full captured excerpt

```
🔧 cpp_layout · bench/shard_replay.cpp
SymbolStats: size 32  (source: pahole (exact))
     0  messages  (8 B)
     8  shares  (8 B)
    16  notional  (8 B)
    24  last_price_ticks  (4 B)
    28  instrument_id  (4 B)
0 of 32 bytes are padding (0%). No member straddles a 64B cacheline.
🔧 cpp_perf
Method: plain timing (perf unavailable) (repeat=9, warmup=1 untimed)
A: mean 0.1903s over 9 run(s) (±0.0016s stderr)
B: mean 0.0795s over 9 run(s) (±0.0004s stderr)
B is 2.39x faster than A (delta 0.1108s > noise gate 0.0041s; significant).
-struct SymbolStats {
+struct alignas(64) SymbolStats {
```

## The source behind the answer

Intel 64 and IA-32 Architectures Software Developer's Manual
§14.2 CACHING TERMINOLOGY · p.3618

> When operating in an MP system, IA-32 processors (beginning with the Intel486 processor) and Intel 64 processors have the ability to snoop other processor’s accesses to system memory and to their internal caches. They use this snooping ability to keep their internal caches consistent both with system memory and with the caches in other processors on the bus. For example, in the Pentium and P6 family processors, if through snooping one processor detects that another processor intends to write to a memory location that it currently has cached in shared state, the snooping processor will invalidate its cache line forcing it to perform a cache line fill the next time it accesses the same memory location.

Retrieved with `search_docs` on 2026-10-26. This document lookup is separate from the recorded session above.

## On your build

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